1. Technical Field
The present disclosure relates to a circuit for preventing a computer power down sequence failure.
2. Description of Related Art
The micro ATX and ATX specifications recommend a 24-pin main connector interface for power supply. This interface incorporates standard ±5V, ±12V, 3.3V, 5V standby, and soft-power signals. Proper implementation of PSON#, 5 VSB, and PG (Power GOOD or Power OK) is required for an ATX-compliant power supply.
During a computer power up sequence, a Southbridge chip of an ATX motherboard receives a PWRBTN# (Power Button) signal and then sends a high level SLP_S3# (S3 Sleep) signal to a PSON# pin of a power connector of an ATX power supply. Then the power supply turns on all of the main power rails including 3.3V, 5V, −5V, 12V, and −12V power rails. After the power rails are powered up and stable, a PG pin of the power connector sends a high level PG signal to the Southbridge. There must be a time delay (100 ms˜500 ms) between the power rails and PG signal to conform to a specified computer power up sequence. After the Southbridge chip receives the high level PG signal, the Southbridge chip sends a reset signal to a CPU. Then, components on the motherboard are all powered up and capable of normally working.
During a computer power down sequence, the PG signal on a PG (Power Good) pin of the Southbridge chip must go to low level before the power rails are powered down. However, the PG signal on the PG (Power Good) pin of the Southbridge chip is often unstable and sometimes does not fall to low level, thereby causing the computer power down sequence to fail.
Therefore, a circuit for quickly setting the PG signal of the Southbridge chip to low level and preventing power down sequence failure is desired.